Synopsys Design Compiler - Tutorial

Here’s a for Synopsys Design Compiler (DC) — focusing on the key features you’ll actually use to synthesize RTL to a gate-level netlist.

Check:

create_clock -period 10 [get_ports clk] set_input_delay 2 -clock clk [all_inputs] set_output_delay 2 -clock clk [all_outputs] synopsys design compiler tutorial

compile_ultra