Xilinx Vivado 2020.2 【90% FRESH】

# From implemented design write_verilog -mode timesim -sdf_anno true -file ./outputs/post_route_sim.v write_sdf -file ./outputs/design.sdf

# post_flow.tcl open_run impl_1 write_checkpoint -force ./results/post_impl.dcp write_verilog -force ./results/post_impl_netlist.v write_bitstream -force ./results/design.bit report_timing_summary -file ./results/timing_summary.rpt report_utilization -file ./results/utilization.rpt report_power -file ./results/power.rpt exit Run: xilinx vivado 2020.2

Then in simulation (Questa/Modelsim/XSIM): xilinx vivado 2020.2